1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a configuration that increases the data read rate.
2. Description of the Prior Art
Since in the past, a quick access to a flash memory has been demanded similar to other forms of memory medium. According to the conventional circuit configuration, since the input impedance on the reference cell array side is kept at a constant level for all times, circumstances arise in which the input impedance on the reference cell array side and the input impedance on the main cell array side do not match with each other for some cell arrays selected on the main cell array side. As a result, it has been very difficult to realize a fast access to the main memory cell array.
FIG. 1 is a circuit diagram showing the configuration of a semiconductor memory device according to Prior Art 1. Of the impedances as seen from I-V conversion circuits (current-to-voltage conversion circuits) 2 and 3, the impedance varies depending upon the selected sector on the main cell array side, whereas it does not vary depending upon the selected sector on the reference cell array side, as indicated in FIGS. 4A-4B.
In order to read data in a cell array 1, a cell array 1 selection signal and a reference cell array selection signal are brought to high level, and a node 500 is connected to a node 700, and a node 600 is connected to an I-V conversion circuit 3.
A cell array N select signal (cell array select signal for controlling a cell array select N-channel transistor (N-ch Tr) corresponding to a cell array other than the cell array 1) goes to low level, and a node 501 and a global bit line 4 go to open state. Then, a row decoder 9 of the cell array 1 selects an arbitrary word line, and its column decoder 10 selects an arbitrary sub-bit line 7. The arbitrary sub-bit line selected is connected to the node 500 via the column decoder 10. A row decoder 11 selects a word line connected to a reference cell gate in the reference cell array. The reference sub-bit line 8 is connected to the node 600 via a dummy decoder 12.
Next, the operation of the Prior Art 1 semiconductor memory device will be described. By the transition of an address transaction director (ATD) signal 2 from high to low level, and the transition of a PRE signal from low to high level in a state at T=0, the I-V conversion circuits 2 and 3 are activated to start cell data read operation. The global bit line 4 and the sub-bit line 7 of the cell array 1, and a reference global bit line 5 and the reference sub-bit line 8 of the reference cell array are charged up by the currents from the I-V conversion circuits 2 and 3, respectively.
To describe the operation with reference to the I-V conversion circuits 2 and 3 in FIG. 2, the output of the NOR circuit goes to high level as a result of transition of the ATD signal from high level to low level. As the output of the NOR circuit goes to high level, the global bit line 4 and the reference global bit line 5 are connected to a power supply via an N-ch Tr 1. In addition, as the PRE signal goes to high level, the global bit line 4 (reference global bit line 5 in the I-V conversion circuit 3) is connected to the power supply.
A precharging circuit in the I-V conversion circuits 2 and 3 is provided for supplementing charge-up of each bit line. By the connection of the node 700 and the reference global bit line 5 to the power supply the potentials at the nodes 500, 700 and 600 go up. When the potential reaches the threshold voltage of NOR circuit in the I-V conversion circuits 2 and 3, the N-ch Trs 2 and 5 in the I-V conversion circuits 2and 3 are turned off. This state represents a state in which the global bit line 4, the sub-bit line 7, the reference global bit line 5 and the reference sub-bit line 8 are fully charged up by the current flowing in the I-V conversion circuits 2 and 3.
According to the conventional circuit configuration, the impedance of the global bit line 4 on the main cell array side and the impedance of the reference global bit lime 5 on the reference cell array side as seen from the I-V conversion circuits 2 and 3 are different as shown in FIG. 4.
FIGS. 9A and 9D are the waveform diagrams showing the waveforms of the current and voltage in respective paths. A current IgsN that flows in the global bit line 4 and a current Igs1 (=Is1) that flows in the sub-bit line 7 start charging of the capacitance of the global bit line 4 and the capacitance of the sub-bit line 7 from T=0 and complete the charging at T=1. When the charging is completed, the current IgsN flowing in the global bit line 4 goes to 0[A]. The current Igs1 flowing in the sub-bit line 7 is the cell current selected in the cell array. A current Im input to the I-V conversion circuit 2 is given by the following formula:
Current Im=IgsN+Igs1
Analogously, in the reference part, a current IgrN flowing in the reference global bit line 5 and a current Igr1 flowing in the reference sub-bit line 8 start charging the capacitance of the reference global bit line 5 and the capacitance of the reference sub-bit line 8 at T=0 and completes the charging at T=1. When the charging is completed, the current IgrN flowing in the reference sub-bit line 8 goes to 0[A]. The current Igr1 flowing in the reference sub-bit line 8 is the cell current selected in the cell array. A current Iref that is input to the I-V conversion circuit 3 is given by the following formula:
Current Iref=IgrN+Igr1.
Each of the charging currents varies according to the impedance as seen from each of the I-V conversion circuits 2 and 3. Since the impedances on the main cell array side and the impedance on the reference cell array side differ as shown in FIGS. 4A-4B, the currents Im and Iref are different. In the state at T=1, the PRE signal changes from high level to low level, and the precharging circuits in the I-V conversion circuits 2 and 3 stop their operations.
Describing the operation by reference to the I-V conversion circuits 2 and 3 in FIG. 2, as a result of transition of the PRE signal to low level the N-ch Tr 4 in the I-V conversion circuits 2 and 3 is turned off, and the global bit line 4 (reference global bit line 5 in the I-V conversion circuit 3) and the power supply go into an open state.
In the state at T=1, the nodes 500, 700 and 600 are fully charged. During the period from T=1 to T=2, it is necessary for the main cell array side to transmit the current of the selected cell to Im. Since the electric charge stored on the global bit line 4 flows into Igs1, the current Im apparently goes to 0[A].
On the reference cell array side, the reference cell current Iref is transmitted to the I-V conversion circuit 3 at T=1. The transmission takes place since the reference global bit line 5 carries no parasitic capacitance and no excess charge is stored on it.
Accordingly, during the stage from T=1 to T=2, the expected current Iref is transmitted to the I-V conversion circuit 3 in its complete form, but the expected current Im is not transmitted to the I-V conversion circuit 2 in its complete form. Consequently, the outputs Vm and Vref of the I-V conversion circuits 2 and 3 give a difference potential which is not expected. If Vm and Vref are compared in this stage, there is a possibility that the comparator circuit 1 cannot output the exact information, which becomes a cause of malfunction.
During the period from T=2 to T=3, the cell current of a cell actually selected by the cell array 1 starts to flow, and the output Vm of the I-V conversion circuit 2 begins to change. It is only at the stage of T=4 that the expected difference potential is brought about between Vm and Vref.
When the difference potential is established, the comparator circuit 1 compares Vm and Vref at the timing when the ATD 1 signal changes from low level to high level, and outputs a low level signal if the potential of Vm is lower than that of Vref, and outputs a high level signal if the potential of Vm is higher than that of Vref. In FIG. 9B, the potential of Vm is lower than that of Vref so that the comparator circuit 1 is outputting a low level signal. The above is a summary of the configuration and the operation of Prior Art 1.
Next, a semiconductor memory device as disclosed in Japanese Patent Applications Laid Open, No. Hei 11-3599 will be described as Prior Art 2.
The semiconductor memory device has two reference bit lines, and is provided with a means for switching between the two reference bit lines in synchronism with the bit line selection on the main cell array side, and a shield due to a power supply line disposed between the reference bit line and the bit line.
According to the semiconductor memory device of Prior Art 2, the interline capacitances for the bit lines and the reference lines as seen from the differential amplifier side are equal, and since the bit line and the reference line exhibit similar behavior even when a disturbance enters from a peripheral element, stabilized data read becomes possible. Moreover, through the formation of a shield it becomes possible to exclude the effect due to the interline capacitance between the bit line and the reference line.
However, in the semiconductor memory device according to Prior Art 1, the impedances of the global bit line 4 and the reference global bit line 5 as seen from the I-V conversion circuits 2 and 3 are different, so that it gives rise to a problem that the comparator circuit 1 may cause malfunctions. Moreover, if it is desired to avoid malfunctions, it is necessary to shift the comparison times of the voltage Vm on the main cell array side and the voltage Vref on the reference cell array side, giving rise to a problem of slow-down of the reading rate.
In the semiconductor memory device of Prior Art 2, it is true that the problem of flow of inexact current in the sense amplifier part, due to the effect of the capacitance between the sub-bit lines in the cell array or the interline capacitance between the sub-bit line and the reference bit line, can surely be eliminated. However, the problems of malfunction in the sense amplifier part due to the difference in the impedances of the global bit line that connects the cell array and the sense amplifier part and the reference global bit line, and the slow-down of the data read operation remain unresolved.
Object of the Invention
It is the object of the present invention to provide a semiconductor memory device which makes it possible to make the input impedance on the main cell array side and the input impedance on the reference cell array side as seen from the I-V conversion circuits 2 and 3 (sense amplifiers) equal with each other.
A semiconductor memory device having a plurality of cell arrays and one reference cell array comprises a first current-to-voltage converting means which converts a cell current input from a cell array into a main cell voltage, a second current-to-voltage converting means which converts a reference cell current input from the reference cell array into a reference cell voltage, global bit lines which connect the first current-to-voltage converting means and the plurality of cell arrays, and a dummy global bit line which connects the second current-to-voltage converting means and the reference cell array, where the impedance of the global bit line and the impedance of the dummy global bit line are equal with each other.
The above-mentioned and other objects, features and advantages of this invention will become more apparent by reference to the following detailed description of the invention taken in conjunction with the accompanying drawings, wherein:
FIG. 1 is a circuit diagram showing the configuration of a semiconductor memory device according to the prior art;
FIG. 2 is a circuit diagram showing the configuration of two I-V conversion circuits;
FIG. 3 is a circuit diagram showing a cell array and a reference cell array;
FIGS. 4A and 4B are circuit diagrams for describing impedance of the wirings of a reading system according to the prior art;
FIG. 5 is a circuit diagram showing the configuration of the semiconductor memory device of the embodiments according to the present invention;
FIGS. 6A and 6B are circuit diagrams for describing the impedances of the wirings of a reading system in the embodiments of the invention;
FIG. 7 is an equivalent circuit of the impedance of a global bit line in a first embodiment of the invention;
FIG. 8 is an equivalent circuit of the impedance of a global bit line in a second embodiment of the invention; and
FIGS. 9A to 9D are waveform diagrams at data read in the prior art and in the embodiments of the invention.